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Add VCU118 Ethernet and flash boot - #124
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Adds support for the AMD/Xilinx VCU118 Evaluation Board (xcvu9p-flga2104-2L-e): - Board wrapper (vcu118_frost.sv) with MMCM clocking, USB-UART console, and DDR4 integration - Floorplanning constraints (vcu118.xdc) confining CPU, caches, and memory subsystem to SLR2 - Configurable CPU clock generator (vcu118_clock.sv) with 200 MHz default baseline and 240 MHz hero target - DDR4 memory initialization engine (vcu118_ddr_init.sv) establishing valid ECC across the 2 GB aperture - Dual-channel DDR4 block design (vcu118_ddr_bd.tcl) targeting onboard Micron MT40A256M16GE-083E component memory - GTY transceiver CPLL CPU clock generator (vcu118_cpu_clock_gty.sv, vcu118_gty_ip.tcl) - Build, programming, and software loading integration (build.py, load_software.py, program_bitstream.tcl) - Comprehensive affirmative board guide, post-route resource utilization breakdown, timing closure metrics, and physical silicon benchmarks (boards/vcu118/README.md) - Root and board summary tables updated (README.md, boards/README.md)
…b and 10Gb networking
- Add default-off GMII_MODE parameter to nic_mac_wrap and nic_top (8:1 XGMII-to-GMII TX serializer and 1:8 GMII-to-XGMII RX deserializer at 125 MHz) and default-off ENABLE_1G_ETH parameter across soc_top, platform_top, frost, and xilinx_frost_subsystem (preserving zero changes to Alveo X3). - Generate license-free Vivado IPs for VCU118: vcu118_nic_gty_wiz (Quad 231 GTYE4_CHANNEL_X1Y48, 10.3125 Gbps) and vcu118_pcs_pma_1g (gig_ethernet_pcs_pma:17.0 in Bank 64 SGMII-over-LVDS mode). - Add vcu118_nic_gty.sv (10Gb QSFP1 Lane 0 wrapper with 150 MHz GTY supervisor) and vcu118_eth1g.sv (autonomous Clause-22 MDIO bootstrap for TI DP83867 PHY_ADDR=0x03 6-wire 625 MHz SGMII + 1G PCS/PMA). - Expose ethernet@40030000 (eth0, 10Gb) and ethernet@40022000 (eth1, 1Gb) in frost_boot_image.py, return -ENODEV quietly when unpopulated, and add Dropbear SSH + udhcpc auto-bringup on eth1. - Verify timing closure at 200 MHz (WNS = +0.004 ns, TNS = 0.000 ns, 0 failing endpoints) and validate on VCU118 silicon: 10Gb QSFP28 GTY PMA loopback (FROST_NET_LOOPBACK_PASS) and 1Gb RJ-45 1000BASE-T link, DHCP, ping, and concurrent SSH + UART login consoles.
… flash boot, and interactive U-Boot - Add 1Gb RJ-45 SGMII Ethernet MAC (0x4002_2000) via TI DP83867 PHY and AMD gig_ethernet_pcs_pma - Add 10Gb QSFP28 Ethernet MAC (0x4003_0000) on GTY Quad 231 (X1Y48) with verified near-end PMA loopback - Add on-chip BRAM Boot ROM (0x0000_0000) loading FSBL into on-chip SRAM (0x0000_4000) with CRC-32 verification - Add FSBL in on-chip SRAM verifying DDR4 calibration and loading OpenSBI, DTB, and U-Boot Proper into DRAM - Add U-Boot Proper (0x8020_0000) with DM_ETH dual-Ethernet drivers, DM_SPI flash control, 3-second console interrupt, and multi-mode boot flows - Update flash memory map to 0x0300_0000 software aperture with dedicated 32 MiB Linux kernel partition - All shared RTL changes strictly gated by ENABLE_1G_ETH != 0 for zero X3 regressions - Zero CHERI references across all code, comments, and documentation
Preserve the contributor commits and merge the board-flow fixes from main. Resolve the board clock, reset and constraint changes together with Ethernet integration, apply repository formatting, and preserve source notices. Update software-build test doubles for the selected initial application. Lint and the fast suite pass.
Keep the default slice-writer inputs identical when the board peripherals are disabled. Test the GMII wire protocol and the secondary NIC, SPI controller and SRAM programmer through the CPU bus.
Require the copper link and full duplex before enabling receive traffic. Keep internal loopback available without a cable. Exercise the status combinations, speed modes and reset through the portable link decoder.
Bound each image to its partition and expected load address. Build the ROM, FSBL, device tree, OpenSBI and pinned U-Boot from repository inputs. Use the managed hardware session for flash programming and distinguish configuration data from software payloads. Recycle failed receive descriptors and enforce SPI transaction, speed and mode handling. Exercise image validation, session cleanup and driver error paths without hardware. Document the firmware and network boot paths and preserve the source notices.
Describe the second NIC only for VCU118 and keep simulation device trees on the default platform. Identify the RJ-45 interface by its device address before starting DHCP and preserve an assigned address. Require SSH keys in the test image. Reject flash-stage loader combinations that cannot execute at the reset vector. Test board selection, interface naming and loader preflight. Update the board and Linux usage, supported interfaces and contributor credit together.
…t ramdisk boot - Add rootfs.uimg build target wrapping the composed initramfs in sw/apps/linux_boot/Makefile - Document Boot Option 4 (TFTP network boot with composed ramdisk) in boards/vcu118/README.md - Embed frost_net10g.ko and S03frost-net10g loader into rootfs.uimg for automated DHCP and SSH
Select the supported flash driver and firmware device-tree option, and check every requested U-Boot setting against the generated configuration. Use four-byte flash addressing and enable conditional command chains. Forward the selected compiler to both boot stages. Allow cable listing without input images, name the FPGA image argument, and correct boot and interface descriptions. Firmware compilation, flash image preparation, lint and the fast suite pass.
Accept the raw initramfs and explicit size used by the documented booti command. Check the command chain requirements alongside the shell selection. The firmware build, configuration validation, lint and fast tests pass.
Merge the contributor ramdisk update without rewriting its commit. Wrap the composed initramfs with a selectable mkimage tool, including the host tool from the pinned U-Boot build, and keep both documented initramfs formats enabled. Test that the wrapper receives the driver modules and startup scripts, and document the matching kernel and network boot commands. Linux boot and firmware tests, configuration validation and lint pass.
Anchor the transmit and receive I/O clock copies to the selected PCS branch. Check that the constraint paths include the RTL branch name. The mapped design loads with exactly one reference pin per clock. Lint and the fast suite pass.
Share application availability between the loader, regression stage selection and the X3 editor picker. Exclude bootrom on X3 and keep it available for VCU118 BRAM execution. Cover both stage lists, default dispatch, invalid explicit selections and editor metadata. Preserve target discovery without an application. Lint and fast Python tests pass.
Require verified ROM and FSBL handoffs from the latest boot attempt, then a U-Boot prompt and a quiet console. Recognize firmware halt, validation and initialization failures. Give bootrom a minimum timeout of 600 seconds and preserve larger caller timeouts. Keep other application verdicts and budgets unchanged. Use a supported string format in the FSBL progress message. Cover partial and stale UART output, restarts, capture outcomes and timeout selection with synthetic transcripts. Lint, fast Python tests and the FSBL build pass.
Accept the secondary Ethernet and flash ports in the TestRIG fixture and hold their outputs idle. Keep device accesses on shadow RAM. Check the fixture parameter and port types against platform_top in the fast suite and verify the idle outputs after each instruction trace.
With random power-up state and an independent CPU clock, the first clock edge could sample the platform's reset path before it settled, letting the NIC leave reset briefly with randomized state. The bench now holds the clocks low until the external reset has settled; the design's checks and randomized state are unchanged. Reproduce the three failing asynchronous programs with the CI seeds and check them and the job's other programs in both memory configurations.
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Integrates John Goodacre's VCU118 Ethernet, flash boot and U-Boot port, superseding #122 with his commits preserved. Adds RJ-45 and QSFP28 networking and the Debian NFS configuration, with boot-image validation, portable firmware builds and application selection for each board. Flash boot checks require verified ROM and first-stage loader handoffs and the interactive U-Boot prompt.
Lint, the fast tests including boot transcripts, the NIC, MAC and PCS simulations, the NIC and DMA programs in BRAM and DDR, Yosys and ASIC synthesis pass.