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vcu118: fix synthesis port tie-offs, flash part check and 4-byte SPI boot - #126
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The upstream merge of the Ethernet PR left the former no-Ethernet stub tie-offs on u_frost_subsystem in place alongside the active NIC wiring. Remove the redundant constant tie-offs to resolve Synth 8-344 errors.
get_cfgmem_parts returns multiple duplicate entries for the MT25QU01G part in Vivado 2024.x/2025.x releases. Deduplicate results before verifying that a single unique flash part is selected.
The VCU118 bitstream exceeds 16 MiB, requiring 4-byte SPI addressing to read from the 128 MiB onboard flash. Enable SPIx4 configuration mode and SPI_32BIT_ADDR so the FPGA successfully boots autonomously from flash.
Print elapsed wall time upon build completion in fpga/build/build.py. Document the SW16 DIP switch configuration for Master SPI flash boot (M[2:0] = 001, ON/OFF/OFF/ON) and SSH public key installation in the VCU118 test initramfs.
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John's #125 with his four commits unchanged, plus one commit that wraps the new build wall-time line so the Lint job's ruff format check passes. Supersedes #125.
get_cfgmem_parts.The pre-commit hooks pass on the changed files.