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vcu118: fix synthesis port tie-offs, modern Vivado flash tool check, and 4-byte SPI boot - #125
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The upstream merge of the Ethernet PR left the former no-Ethernet stub tie-offs on u_frost_subsystem in place alongside the active NIC wiring. Remove the redundant constant tie-offs to resolve Synth 8-344 errors.
get_cfgmem_parts returns multiple duplicate entries for the MT25QU01G part in Vivado 2024.x/2025.x releases. Deduplicate results before verifying that a single unique flash part is selected.
The VCU118 bitstream exceeds 16 MiB, requiring 4-byte SPI addressing to read from the 128 MiB onboard flash. Enable SPIx4 configuration mode and SPI_32BIT_ADDR so the FPGA successfully boots autonomously from flash.
Print elapsed wall time upon build completion in fpga/build/build.py. Document the SW16 DIP switch configuration for Master SPI flash boot (M[2:0] = 001, ON/OFF/OFF/ON) and SSH public key installation in the VCU118 test initramfs.
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Summary
This PR addresses three post-merge issues on the VCU118 evaluation board target following PR #124, adds build wall-time reporting, and documents the hardware Master SPI mode switch.
Key Changes
Fix duplicate NIC port connections in board top (
boards/vcu118/vcu118_frost.sv).i_nic_tx_clk(1'b0), etc.) remained in place onu_frost_subsystemalongside the newly added active NIC wiring (.i_nic_tx_clk(nic_tx_clk)).[Synth 8-344] connection to input port 'i_nic_tx_clk' is duplicated.Deduplicate flash parts in
fpga/flash/program_flash.tclget_cfgmem_parts mt25qu01g-spi-x1_x2_x4returns a list with duplicate entries (length 10). The script strictly asserted[llength $part] == 1and threw an error.[lsort -unique [get_cfgmem_parts ...]]prior to the length check so modern Vivado releases successfully select the part.Enable 4-byte SPI addressing in
boards/vcu118/constr/vcu118.xdcCONFIG_MODE SPIx4andBITSTREAM.CONFIG.SPI_32BIT_ADDR Yesto match the Alveo X3 board configuration constraints, allowing the FPGA to boot autonomously from the 128 MiB MT25QU01G flash.Build wall-time reporting and documentation
Build wall time: Xh Ym Zs) upon completion infpga/build/build.py.ON / OFF / OFF / ON, M[2:0] = 001), pin readback viaREGISTER.CONFIG_STATUS.SLR0.*, and SSH public key installation inboards/vcu118/README.md.Verification
pytest tests/test_vcu118_flash.py tests/test_uboot_drivers.py tests/test_fpga_build.py(420/420 passed).vcu118_frost.svwith zero duplicate pin connection warnings.