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Return zero for empty memory-mapped FIFO reads - #133
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Mask each empty FIFO lane before capturing the MMIO response in the SoC and RVFI platform. Preserve the addressed pop and response latency. Document the MMIO contract and distinguish FIFO pops from RAM reads. Exercise arbitrary empty data, independent lanes, the last valid word, and held responses in the SoC bus bench with both clock configurations. The empty-read check rejects the unmasked RTL.
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Reading an empty memory-mapped FIFO returned whatever its RAM held at the read pointer, which after power-up is uninitialized. packet_parser's startup drain took that word's low byte as a string length, so it could make up to 16,384 reads before its timed parse, depending on the RAM's power-up contents. Each 32-bit lane of the FIFO register pair now reads as zero while its FIFO is empty. Non-empty reads and pops are unchanged. fifo.h, the MMIO section of hw/rtl/README.md and the FIFO comments describe the behavior.
The soc_axil bench checks empty, non-empty and mixed lanes with random power-up RAM contents, and fails on the old RTL. packet_parser's first run takes about 63,000 cycles instead of 129,000 to 426,000. Lint, the fast tests, synthesis and both programs that use the FIFOs pass, and BRAM CoreMark is unchanged.
This is the cause of main's packet_parser DDR timeout after #129. With that job's seeds, the first run hits the 500,000-cycle limit on main and finishes in about 105,000 cycles with this change.