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fpga: reject implicit nets in synthesis - #128
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The NIC engines' packer and unpacker connections, the APLIC read capture in soc_top and the async FIFO's write-side pointer synchronizer named nets declared further down their modules. Vivado assumed implicit nets for them and, because each use was in the module's own scope, bound them to the later declarations, so the logic was unaffected. Declare them before their first use so that synthesis can reject implicit nets.
Verilator binds a name used before its declaration to the later declaration. Inside a generate block, Vivado instead gives the use its own implicit net, so either the use or the declaration is left undriven and Vivado ties the logic it feeds to constants, unlike any Verilator simulation. Top-level synthesis now treats Synth 8-11241, Vivado's implicit-net message, as an error. The troubleshooting table describes the error, and a test keeps the setting ahead of synthesis.
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Verilator binds a name used before its declaration to the later declaration. Inside a generate block, Vivado instead gives the use its own implicit net, so either the use or the declaration is left undriven and the hardware differs from every Verilator simulation. The build accepted this without complaint.
X3 synthesis passes with the check, also with the VCU118's 1G Ethernet logic enabled, and main without the declaration moves stops on it. The VCU118 build itself was not run. Lint, the build-flow tests and the NIC, APLIC and async FIFO benches pass.