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Shorten recovery, reset, AXI read and fetch tag logic paths - #127
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Enable RTL assertions for the reset entries with common and independent CPU clocks. Document the default and exercise both registry invocations. Verify formatting and fast Python checks.
Include IMSIC in the DMMU's independent PMA reference. Exercise loads, stores, atomic faults, superpage offsets and early-store lookups at its boundaries, including SQ routing for ordinary stores. Validate both memory-aperture configurations with assertions and run lint and fast Python checks.
Sample the execution hold from early recovery and fatal stop on their shared register edge. Preserve the early-only consumers and immediate fatal retirement and memory gates. Full flush cancels early recovery; reset clears the combined hold. Prove the hold identity for arbitrary binary inputs and cover reset, flush and fatal-request overlaps. Run asserted recovery, debug, reset, program and synthesis regressions.
Capture R data when a valid beat arrives and the buffer is vacant or its selected read is ready to leave. Keep response validity, ownership and reset draining on their qualified handshakes. Add an independent payload-lifetime proof and exercise response stalls, replacement, unknown IDs and resets with buffered traffic.
Assert CPU reset asynchronously with fabric or registered core reset. Release it on the following shared clock edge. Request fanout replication for the CPU reset register. Independent-clock reset handling and fabric draining use their separate reset controls. Extend stopped-clock and repeated-reset checks to cover CPU release and core-reset edges. Validate random startup, asynchronous operation, debug access, program regressions, synthesis, and timed BRAM benchmark identity.
Use the stored line bits above the direct-cache index for hit checks. Each valid entry carries the index of its fill address. Error records compare their full line identities. Assert that valid entries carry the selected index and compare each indexed hit with a complete-tag reference. Keep fill, invalidation, word selection, cache capacity and fetch response cycles unchanged.
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Four changes that shorten logic paths in the CPU: the execution hold from early recovery and fatal stop is sampled on one shared register, AXI read data capture is separated from response ownership, CPU reset release on the shared clock goes through its own register, and the direct fetch cache compares only the stored line bits above its index. CPU reset release takes one more cycle at startup; CoreMark's timed cycle counts are unchanged.
Two test additions come along: the DDR reset regressions run with RTL assertions enabled, and the DMMU tests cover the IMSIC window's translation boundaries.
New hold-identity and AXI payload-lifetime proofs, the recovery, AXI, reset, debug and fetch benches in both clock modes, lint, the fast tests and synthesis pass.