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Add Apple arm64e_x1 target feature (FEAT_PAuth_LR and FEAT_CPA2) - #9653
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Codecov Report❌ Patch coverage is Additional details and impacted files@@ Coverage Diff @@
## main #9653 +/- ##
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+ Coverage 72.93% 73.10% +0.17%
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Files 264 266 +2
Lines 83060 83555 +495
Branches 20399 20541 +142
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+ Hits 60577 61085 +508
- Misses 16117 16123 +6
+ Partials 6366 6347 -19 ☔ View full report in Codecov by Harness. 🚀 New features to boost your workflow:
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Add the `arm64e` target feature (`Target::ARM64e` /
`halide_target_feature_arm64e`) for 64-bit Darwin ARM targets (`ios` and
`macos`), enabling Apple's Pointer Authentication (PAC) ABI:
- Target definition & validation:
- Detect `__arm64e__` in `calculate_host_target()` on Apple platforms.
- Validate that `arm64e` is only used with 64-bit ARM on `ios` or `macos`.
- Imply `armv83a` and `arm_fp16` when `arm64e` is enabled, and treat
`ARM64e` as an ABI-matching feature in `get_runtime_compatible_target()`.
- Expose `TargetFeature.ARM64e` in Python bindings.
- Triple & CPU selection:
- Emit the `AArch64SubArch_arm64e` sub-architecture in
`get_triple_for_target()` for `ios` and `macos` instead of overriding the
macOS arch name to `arm64`.
- Default `mcpu_target()` to `apple-a12` on iOS when `arm64e` is enabled.
- LLVM PAC codegen & JIT support:
- Add `ptrauth-returns`, `ptrauth-calls`, `ptrauth-auth-traps`,
`ptrauth-indirect-gotos`, and `aarch64-jump-table-hardening` function
attributes on non-intrinsic functions when `triple.isArm64e()`.
- Sign non-callee function references via `llvm::ConstantPtrAuth` (`IA` key 0,
discriminator 0, matching Darwin userspace `arm64e`) and attach `"ptrauth"`
operand bundles to indirect call sites across AOT and JIT modules.
- Sign JIT-resolved function addresses via `llvm::orc::ExecutorAddr::toPtr`
when building on `ptrauth_calls` hosts.
- Add target, cross-compilation, Python binding, and Mach-O / assembly / IR
codegen tests.
Co-authored-by: Gemini 3 <gemini-code-assist@google.com>
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- Map `arm64e` on 64-bit `ios` and `macos` to `arm-64-(ios|macos)-arm64e` in `HalideTargetHelpers.cmake` (both `_Halide_cmake_target` and native single-arch `arm64e` host builds in `_Halide_host_target`). - Support `arm-64-(ios|macos|osx)-arm64e` in `_Halide_set_osx_arch`, `FEATURES[<triple>]`, `_Halide_validate_multitarget`, `_Halide_is_crosscompiling`, and multi-arch `add_halide_runtime` slice filtering, and pin host generator `OSX_ARCHITECTURES` to `Halide_HOST_TARGET` when building multi-arch or consuming an imported `Halide::Generator` with a different Darwin ABI slice. - Emit fat `arm64 + arm64e` `iphoneos` slices in `apps/HelloiOS` (`ARCHS = "$(ARCHS_STANDARD) arm64e"`), and add macOS CI steps building and verifying both `HelloiOS` (`iphoneos` `arm64 + arm64e`) and `test/integration/xc` (`CMAKE_OSX_ARCHITECTURES="arm64;arm64e"`). - Document `arm-64-(ios|macos)-arm64e` CMake triples and `HelloiOS` slices. Co-authored-by: Gemini 3 <gemini-code-assist@google.com>
- Initialize all words of `runtime_features` to `~uint64_t{0}` in
`compile_multitarget()` and add `Target::ARM64e` to `must_match_features` so
high-word target features (>= 64) are preserved on the shared runtime and
mixed-PAC-ABI multitarget builds fail cleanly.
- Extract `CodeGen_LLVM::apply_target_options()` and invoke it when
`JITSharedRuntime::get()` creates a standalone runtime module without
`for_module`, and assert matching host/target `arm64e` PAC ABI in both
`get_jit_target_from_environment()` and `compile_module_impl()`.
- Reject `arm64e` combined with `simulator` in `Target::validate_features()`.
- Preserve ascending `armv8*` lower-bound semantics for non-`arm64e` targets in
`Target::get_arm_v8_lower_bound()` while clamping `arm64e` to at least `83`,
and strip implied `armv8a`..`armv83a` bits from `arm64e` GCD outputs in
`Target::get_runtime_compatible_target()`.
- Add `arm64e` static library, `compile_multitarget`, `with_implied_features()`
GCD, and `arm-64-ios-arm64e-simulator` tests.
Co-authored-by: Gemini 3 <gemini-code-assist@google.com>
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Preserving high-word (>= 64) common features on runtime_target in compile_multitarget() exposed that runtime_target left vector_bits == 0, tripping CodeGen_ARM's SVE2 vector_bits assertion when all subtargets share SVE2 (e.g. host-profile-* on SVE2 ARM64 Linux). Propagate vector_bits when uniform across all subtargets, clear SVE/SVE2/AVX10_1 when runtime_target.vector_bits == 0 (mixed vector_bits across subtargets), and clear SME2 when intersecting subtarget features clears all SME_SVL* bits. Add cross-compilation regression tests in compile_to_multitarget.cpp. Co-authored-by: Gemini 3 <gemini-code-assist@google.com>
Add the `arm64e_x1` target feature (`Target::ARM64eX1` /
`halide_target_feature_arm64e_x1`) for Apple's `arm64e.x1` ABI slice on 64-bit
Darwin ARM (`ios` and `macos`):
- Target definition, host detection, & validation:
- Detect `__arm64e_x1__` or active `pauth-lr` return-address signing
(`__ARM_FEATURE_PAUTH_LR` with `__ARM_FEATURE_PAC_DEFAULT & (1 << 3)`) under
`__arm64e__` in `calculate_host_target()`, and enforce matching 3-level PAC
ABI (`none` / `arm64e` / `arm64e_x1`) in JIT validation.
- Validate that `arm64e_x1` is only used with 64-bit ARM on `ios` or `macos`
and cannot be combined with `simulator`.
- Imply `arm64e`, `armv87a`, `arm_fp16`, and `arm_dot_prod` (matching LLVM's
`HasV8_7aOps` baseline on Apple CPUs without enabling `FEAT_MOPS`), treat
`ARM64eX1` as an ABI-matching feature in `get_runtime_compatible_target()`
and `compile_multitarget()`, and strip implied `arm64e` and `armv8a`..`armv87a`
bits from `arm64e_x1` GCD outputs.
- Expose `TargetFeature.ARM64eX1` in Python bindings.
- CPU, feature attributes, & FEAT_CPA codegen:
- Select `apple-m5` (currently the newest Apple CPU model in LLVM) in
`CodeGen_ARM::mcpu_target()` on `ios` and `macos` when `arm64e_x1` is
enabled, and append `+pauth-lr` and `+cpa` in `mattrs()`.
- Record an explicit `"halide_arm64e_x1"` module flag in
`CodeGen_LLVM::apply_target_options()` (and preserve it in
`clone_target_options()`), using it to emit `"branch-protection-pauth-lr"`
on non-intrinsic functions (`pacibsppc` / `retabsppc`) and to patch Darwin
Mach-O `mach_header_64.cpusubtype` to `0x8000000c`
(`CPU_SUBTYPE_ARM64E_X1 | 0x80000000`).
- Enable `aarch64-use-featcpa-codegen` after `Initialize*Target()` via
`cl::getRegisteredOptions()` when unset (falling back to
`cl::ParseCommandLineOptions(..., &llvm::nulls())` for LLVM 24+ TableGen
`LibraryOptions`) and before `HL_LLVM_ARGS` so `+cpa` lowers pointer
indexing to `addpt` / `subpt` / `maddpt`.
- Clear opportunistic non-`musttail` tail-call markers on indirect ptrauth
`CallInst`s when `arm64e_x1` is active, since LLVM's AArch64 `AUTH_TCRETURN`
lowering does not yet support `branch-protection-pauth-lr`.
- CMake & tests:
- Support `arm64e.x1` / `arm-64-(ios|macos|osx)-arm64e_x1` in
`HalideTargetHelpers.cmake`, `HalideGeneratorHelpers.cmake`, and
`doc/HalideCMakePackage.md`.
- Extend target, cross-compilation, Python binding, static library, and
multitarget codegen tests.
Co-authored-by: Gemini 3 <gemini-code-assist@google.com>
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- Wrap the arm64e/arm64e.x1 if-condition in cmake/HalideTargetHelpers.cmake to satisfy the cmtk pre-commit formatter. - Use cl::Option::addOccurrence() instead of downcasting cl::Option* via static_cast<cl::opt<bool> *> in CodeGen_LLVM::initialize_llvm() to satisfy clang-tidy (cppcoreguidelines-pro-type-static-cast-downcast) under -fno-rtti. Co-authored-by: Gemini 3 <gemini-code-assist@google.com>
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Adds the
arm64e_x1target feature (Target::ARM64eX1/halide_target_feature_arm64e_x1) for Apple'sarm64e.x1Mach-O architecture slice (FEAT_PAuth_LRand Checked Pointer ArithmeticFEAT_CPA2, introduced in Xcode 27).Related discussion: #9651
(Note: Stacked on #9652; marked as draft until #9652 lands so the diff isolates the
arm64e_x1commit.)Details
halide_target_feature_arm64e_x1/Target::ARM64eX1/hl.TargetFeature.ARM64eX1("arm64e_x1"), valid onarm-64-iosandarm-64-macos.__arm64e_x1__/__ARM_FEATURE_PAUTH_LRunder__arm64e__incalculate_host_target().arm64e,armv87a,arm_fp16, andarm_dot_prod(matching LLVM'sHasV8_7aOpsbaseline on Apple CPUs without enablingFEAT_MOPS), and addsARM64eX1tomatching_featuresinget_runtime_compatible_target().apple-m5(currently the newest Apple CPU model in LLVM) inCodeGen_ARM::mcpu_target()on bothiosandmacoswhenarm64e_x1is set, and appends+pauth-lrand+cpainCodeGen_ARM::mattrs()."branch-protection-pauth-lr"on non-intrinsic functions when+pauth-lris present so function prologues/epilogues emitpacibsppc/retabsppc.-aarch64-use-featcpa-codegen=trueinCodeGen_LLVM::initialize_llvm()after target registration (with&llvm::nulls()so it remains non-fatal if a future LLVM version removes the flag) so pointer arithmetic lowers toaddpt/subpt/maddpt.musttailtail-call markers on indirect ptrauthCallInsts whenarm64e_x1is enabled, as LLVM's AArch64AUTH_TCRETURNlowering does not yet supportbranch-protection-pauth-lr.compile_llvm_module_to_object()to stampmach_header_64.cpusubtype = 0x8000000c(CPU_SUBTYPE_ARM64E_X1 | 0x80000000) on Darwinarm64eMach-O object outputs compiled with+cpa.Testing
test/correctness/target.cpp,python_bindings/halide/test/correctness/target.py,test/correctness/cross_compilation.cpp, andtest/correctness/arm64e_codegen.cpp(verifyingapple-m5,pacibsppc,retabsppc,addpt, and Mach-Ocpusubtype == 0x8000000cfor both pipeline and standalone runtime objects).Checklist
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