[phix33]

Your checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

On v5, the Sparc integer ldd and std fail to decode, as shown below:

$ cstool sparc d83863d8
ERROR: invalid assembly code
$ cstool sparc d8184002
ERROR: invalid assembly code

These should be std %o4, [%g1+0x3d8] and ldd [%g1+%g2], %o4. next decodes them. Believe the v5 decoder table was generated from an LLVM version that had no integer LDD/STD (so no table entries to fix).

Resolved by:

• When the generated table fails, Sparc_getInstruction now tries decodeIntPairMem. It only accepts op=3 with op3 0x03 (LDD) or 0x07 (STD), so a word the table already decodes cannot change.
• There are four new internal opcodes (SP_{LDD,STD}{ri,rr}), appended after the existing ones, with mapping entries to the existing SPARC_INS_LDD and SPARC_INS_STD. Instructions printed via printSparcAliasInstr and I didn't change the public API.
• Also, an odd register pair is rounded down (just like LLVM and next do).

Note that I chose this over editing the generated decoder table as inserting entries there would move about 400 offsets.

Test plan

Eight lines in suite/MC/Sparc/sparc-mem-instructions.s.cs, using the same operands as the existing ld/st lines plus the odd register case. Can confirm all eight fail before this change.

Closing issues

None filed.