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PowerPC: restore fcmpo instruction definition #3052

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95b309d
PowerPC: fix undefined class reference in PPCInstrHTM.td
StilesCrisis Aug 30, 2026
eed8747
PowerPC: restore fcmpo instruction definition
StilesCrisis Aug 30, 2026
f49c8ac
PowerPC: regenerate tables for fcmpo support
StilesCrisis Aug 30, 2026
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4,173 changes: 2,088 additions & 2,085 deletions arch/PowerPC/PPCGenAsmWriter.inc
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4,140 changes: 2,071 additions & 2,069 deletions arch/PowerPC/PPCGenDisassemblerTables.inc
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2,838 changes: 1,421 additions & 1,417 deletions arch/PowerPC/PPCGenInstrInfo.inc
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31 changes: 19 additions & 12 deletions arch/PowerPC/PPCMappingInsn.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -1474,7 +1474,7 @@
},

{
PPC_CMPD, PPC_INS_CMPD,
PPC_CMPD, PPC_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
Expand All @@ -1495,7 +1495,7 @@
},

{
PPC_CMPLD, PPC_INS_CMPLD,
PPC_CMPLD, PPC_INS_CMPL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
Expand All @@ -1509,14 +1509,14 @@
},

{
PPC_CMPLW, PPC_INS_CMPLW,
PPC_CMPLW, PPC_INS_CMPL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},

{
PPC_CMPLWI, PPC_INS_CMPLWI,
PPC_CMPLWI, PPC_INS_CMPLI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
Expand All @@ -1530,14 +1530,14 @@
},

{
PPC_CMPW, PPC_INS_CMPW,
PPC_CMPW, PPC_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},

{
PPC_CMPWI, PPC_INS_CMPWI,
PPC_CMPWI, PPC_INS_CMPI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
Expand Down Expand Up @@ -4007,6 +4007,13 @@
#endif
},

{
PPC_FCMPOS, PPC_INS_FCMPO,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},

{
PPC_FCMPUD, PPC_INS_FCMPU,
#ifndef CAPSTONE_DIET
Expand Down Expand Up @@ -8075,21 +8082,21 @@
},

{
PPC_RLDICL, PPC_INS_RLDICL,
PPC_RLDICL, PPC_INS_CLRLDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},

{
PPC_RLDICL_32_64, PPC_INS_RLDICL,
PPC_RLDICL_32_64, PPC_INS_CLRLDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},

{
PPC_RLDICLo, PPC_INS_RLDICL,
PPC_RLDICLo, PPC_INS_CLRLDI,
#ifndef CAPSTONE_DIET
{ 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
#endif
Expand Down Expand Up @@ -8159,7 +8166,7 @@
},

{
PPC_RLWINM, PPC_INS_RLWINM,
PPC_RLWINM, PPC_INS_CLRLWI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
Expand All @@ -8180,7 +8187,7 @@
},

{
PPC_RLWINMo, PPC_INS_RLWINM,
PPC_RLWINMo, PPC_INS_CLRLWI,
#ifndef CAPSTONE_DIET
{ 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
#endif
Expand Down Expand Up @@ -11456,7 +11463,7 @@
},

{
PPC_XORI, PPC_INS_XORI,
PPC_XORI, PPC_INS_XNOP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
Expand Down
78 changes: 39 additions & 39 deletions arch/PowerPC/PPCMappingInsnName.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -256,6 +256,7 @@
"dcbtstt", // PPC_INS_DCBTSTT,
"dcbtt", // PPC_INS_DCBTT,
"dcbz", // PPC_INS_DCBZ,
"dcbz_l", // PPC_INS_DCBZ_L,
"dcbzep", // PPC_INS_DCBZEP,
"dcbzl", // PPC_INS_DCBZL,
"dcbzlep", // PPC_INS_DCBZLEP,
Expand Down Expand Up @@ -537,6 +538,7 @@
"fcfids", // PPC_INS_FCFIDS,
"fcfidu", // PPC_INS_FCFIDU,
"fcfidus", // PPC_INS_FCFIDUS,
"fcmpo", // PPC_INS_FCMPO,
"fcmpu", // PPC_INS_FCMPU,
"fcpsgn", // PPC_INS_FCPSGN,
"fctid", // PPC_INS_FCTID,
Expand Down Expand Up @@ -853,6 +855,43 @@
"popcntb", // PPC_INS_POPCNTB,
"popcntd", // PPC_INS_POPCNTD,
"popcntw", // PPC_INS_POPCNTW,
"ps_abs", // PPC_INS_PS_ABS,
"ps_add", // PPC_INS_PS_ADD,
"ps_cmpo0", // PPC_INS_PS_CMPO0,
"ps_cmpo1", // PPC_INS_PS_CMPO1,
"ps_cmpu0", // PPC_INS_PS_CMPU0,
"ps_cmpu1", // PPC_INS_PS_CMPU1,
"ps_div", // PPC_INS_PS_DIV,
"ps_madd", // PPC_INS_PS_MADD,
"ps_madds0", // PPC_INS_PS_MADDS0,
"ps_madds1", // PPC_INS_PS_MADDS1,
"ps_merge00", // PPC_INS_PS_MERGE00,
"ps_merge01", // PPC_INS_PS_MERGE01,
"ps_merge10", // PPC_INS_PS_MERGE10,
"ps_merge11", // PPC_INS_PS_MERGE11,
"ps_mr", // PPC_INS_PS_MR,
"ps_msub", // PPC_INS_PS_MSUB,
"ps_mul", // PPC_INS_PS_MUL,
"ps_muls0", // PPC_INS_PS_MULS0,
"ps_muls1", // PPC_INS_PS_MULS1,
"ps_nabs", // PPC_INS_PS_NABS,
"ps_neg", // PPC_INS_PS_NEG,
"ps_nmadd", // PPC_INS_PS_NMADD,
"ps_nmsub", // PPC_INS_PS_NMSUB,
"ps_res", // PPC_INS_PS_RES,
"ps_rsqrte", // PPC_INS_PS_RSQRTE,
"ps_sel", // PPC_INS_PS_SEL,
"ps_sub", // PPC_INS_PS_SUB,
"ps_sum0", // PPC_INS_PS_SUM0,
"ps_sum1", // PPC_INS_PS_SUM1,
"psq_l", // PPC_INS_PSQ_L,
"psq_lu", // PPC_INS_PSQ_LU,
"psq_lux", // PPC_INS_PSQ_LUX,
"psq_lx", // PPC_INS_PSQ_LX,
"psq_st", // PPC_INS_PSQ_ST,
"psq_stu", // PPC_INS_PSQ_STU,
"psq_stux", // PPC_INS_PSQ_STUX,
"psq_stx", // PPC_INS_PSQ_STX,
"ptesync", // PPC_INS_PTESYNC,
"qvaligni", // PPC_INS_QVALIGNI,
"qvesplati", // PPC_INS_QVESPLATI,
Expand Down Expand Up @@ -1690,42 +1729,3 @@
"xxspltib", // PPC_INS_XXSPLTIB,
"xxspltw", // PPC_INS_XXSPLTW,
"xxswapd", // PPC_INS_XXSWAPD,

"dcbz_l", // PPC_INS_DCBZ_L,
"psq_l", // PPC_INS_PSQ_L,
"psq_lu", // PPC_INS_PSQ_LU,
"psq_lux", // PPC_INS_PSQ_LUX,
"psq_lx", // PPC_INS_PSQ_LX,
"psq_st", // PPC_INS_PSQ_ST,
"psq_stu", // PPC_INS_PSQ_STU,
"psq_stux", // PPC_INS_PSQ_STUX,
"psq_stx", // PPC_INS_PSQ_STX,
"ps_abs", // PPC_INS_PS_ABS,
"ps_add", // PPC_INS_PS_ADD,
"ps_cmpo0", // PPC_INS_PS_CMPO0,
"ps_cmpo1", // PPC_INS_PS_CMPO1,
"ps_cmpu0", // PPC_INS_PS_CMPU0,
"ps_cmpu1", // PPC_INS_PS_CMPU1,
"ps_div", // PPC_INS_PS_DIV,
"ps_madd", // PPC_INS_PS_MADD,
"ps_madds0", // PPC_INS_PS_MADDS0,
"ps_madds1", // PPC_INS_PS_MADDS1,
"ps_merge00", // PPC_INS_PS_MERGE00,
"ps_merge01", // PPC_INS_PS_MERGE01,
"ps_merge10", // PPC_INS_PS_MERGE10,
"ps_merge11", // PPC_INS_PS_MERGE11,
"ps_mr", // PPC_INS_PS_MR,
"ps_msub", // PPC_INS_PS_MSUB,
"ps_mul", // PPC_INS_PS_MUL,
"ps_muls0", // PPC_INS_PS_MULS0,
"ps_muls1", // PPC_INS_PS_MULS1,
"ps_nabs", // PPC_INS_PS_NABS,
"ps_neg", // PPC_INS_PS_NEG,
"ps_nmadd", // PPC_INS_PS_NMADD,
"ps_nmsub", // PPC_INS_PS_NMSUB,
"ps_res", // PPC_INS_PS_RES,
"ps_rsqrte", // PPC_INS_PS_RSQRTE,
"ps_sel", // PPC_INS_PS_SEL,
"ps_sub", // PPC_INS_PS_SUB,
"ps_sum0", // PPC_INS_PS_SUM0,
"ps_sum1", // PPC_INS_PS_SUM1,
1 change: 1 addition & 0 deletions include/capstone/ppc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -877,6 +877,7 @@ typedef enum ppc_insn {
PPC_INS_FCFIDS,
PPC_INS_FCFIDU,
PPC_INS_FCFIDUS,
PPC_INS_FCMPO,
PPC_INS_FCMPU,
PPC_INS_FCPSGN,
PPC_INS_FCTID,
Expand Down
2 changes: 1 addition & 1 deletion suite/synctools/tablegen/PPC/PPCInstrHTM.td
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ def HTM_get_imm : SDNodeXForm<imm, [{

let hasSideEffects = 1, usesCustomInserter = 1 in {
def TCHECK_RET : Pseudo<(outs gprc:$out), (ins), "#TCHECK_RET", []>;
def TBEGIN_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>;
def TBEGIN_RET : Pseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>;
}


Expand Down
9 changes: 7 additions & 2 deletions suite/synctools/tablegen/PPC/PPCInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2322,8 +2322,13 @@ let isCompare = 1, hasSideEffects = 0 in {
}
}
let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations.
//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
// "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
let isCompare = 1, hasSideEffects = 0 in {
def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
"fcmpo $crD, $fA, $fB", IIC_FPCompare>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
"fcmpo $crD, $fA, $fB", IIC_FPCompare>;
}
let isCompare = 1, hasSideEffects = 0 in {
def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
Expand Down
5 changes: 4 additions & 1 deletion suite/synctools/tablegen/PPC/PPCScheduleP9.td
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Expand Up @@ -33,7 +33,10 @@ def P9Model : SchedMachineModel {
// A dispatch group is 6 instructions.
let LoopMicroOpBufferSize = 60;

let CompleteModel = 1;
// FCMPOS/FCMPOD (restored fcmpo) have no P9 scheduling entry in this
// vendored snapshot, so the model can no longer claim completeness.
// Timing data isn't used for disassembler-table generation.
let CompleteModel = 0;

// Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
// Engine) on Power 9.
Expand Down
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